1. Field of the Invention
The present invention generally relates to semiconductor memory devices using ferroelectric, and particularly relates to a ferroelectric semiconductor memory device with reduced power consumption.
2. Description of the Related Art
Ferroelectric random access memory devices (FRAM) employ ferroelectric as memory cells, and are non-volatile memories that store information as a position of electron inside the crystal structure of ferroelectric.
In DRAMs (dynamic random access memories), either a HIGH voltage or a LOW voltage representing record data is applied to one node of a memory capacitor, so that electrical charge is stored as data between this node and the other node serving as a ground node. In contrast, FRAM data recording is not accomplished by merely applying a HIGH voltage or a LOW voltage to one node of a ferroelectric device. In order to store information, it is necessary to apply a positive-voltage pulse signal to a node of a ferroelectric device while applying a data voltage to another node of the ferroelectric device.
The node to which the positive-voltage pulse signal is applied at the time of data writing is referred to as a plate, which is connected to a plate line for controlling the plate voltage. When a word line is selected, a plate line corresponding to the activated word line is selectively activated, thereby writing data in the selected memory cell.
Data-write operation in FRAMs is substantially the same as data-write operation of DRAMs, except for control of the plate voltage. In brief, a work line is activated to make cell transistors conductive, so that data on the bit lines are written in memory cells through the cell transistors, followed by deactivating the word line after data writing so as to make the cell transistors nonconductive. In FRAMs, a plate line is selectively activated simultaneously with selection of a word line, thereby accomplishing data writing in the ferroelectric memory cells.
FIG. 1 is a block diagram of a typical ferroelectric semiconductor memory device.
An FRAM 510 of FIG. 1 includes an address processing unit 511, a data input/output unit 512, a control unit 513, a word decoder 514, a plate decoder 515, a column decoder 516, a cell circuit 517, and a sense amplifier unit 518.
The cell circuit 517 includes a plurality of cells arranged in a matrix form where the cells are based on ferroelectric memory devices. Further, the cell circuit 517 includes circuitry and wires used for specifying addresses and transferring data when 1-bit data is read from or written in each cell.
The address processing unit 511 is comprised of circuits such as address buffers, address pre-decoders, and so on. The address processing unit 511 receives address signals from an exterior of the device, and supplies the signals to the word decoder 514, plate decoder 515, and the column decoder 516 at appropriate timings.
The data input/output unit 512 is comprised of circuits such as data buffers, and supplies data to the sense amplifier unit 518 at appropriate timings as the data is received from the exterior of the device. Further, the data input/output unit 512 outputs data to the exterior of the device at appropriate timings as the data is read from the cell circuit 517 via the sense amplifier unit 518. The sense amplifier unit 518 amplifies the data to be written, and supplies the amplified data to the cell circuit 517. Also, the sense amplifier unit 518 amplifies data read from the cell circuit 517.
The control unit 513 includes circuits such as control-signal buffers, a command decoder, etc., and receives control signals and a clock signal from the exterior of the device. The control unit 513 decodes a command represented by the control signals, and controls operation and timing of each circuit unit provided in the FRAM 510. Namely, the control unit 513 supplies clock signals and timing signals to each circuit unit of the FRAM 510, so that each circuit unit operates at appropriate timing, thereby achieving data-read/data-write operation of the FRAM 510.
The word decoder 514 decodes a row address supplied from the address processing unit 511, and selectively activates one of the word lines WL corresponding to the row address. As a result, cell transistors connected to the activated word line WL become conductive, so that data-read/data-write operation is conducted with respect to the memory cells of the selected word address.
The plate decoder 515 decodes the row address supplied from the address processing unit 511, and selectively activates one of the plate lines PL corresponding to the row address. In FRAMs, data writing is carried out by applying a HIGH voltage to a node of a ferroelectric device connected to the plate line PL while applying a data voltage of either HIGH or LOW to the other node of the ferroelectric device. Concurrently with the word selection by the word line WL, the plate line PL is selectively activated at a position corresponding to the activated word line WL, thereby achieving data writing in the selected memory cells.
The column decoder 516 decodes a column address supplied from the address processing unit 511, and selectively activates one of the column lines corresponding to the column address. As a result, a corresponding column transistor becomes conductive, connecting a corresponding sense amplifier of the sense amplifier unit 518 to the data input/output unit 512.
In the case of data-read operation, data are read from memory cells connected to the activated word line WL, and appear on bit lines. The sense amplifier unit 518 then amplifies the data on the bit lines. The amplified data is read from a sense amplifier corresponding to the activated column line, and is supplied to the data input/output unit 512. In the case of data-write operation, in the manner reverse to the data-read operation, data is supplied from the data input/output unit 512 to a sense amplifier that is selected by the activated column line. When a word line WL is activated, a memory cell connected to the activated word line WL receives data through bit lines from the sense amplifier unit 518. When this happens, a plate line PL connected to the memory cell is selectively activated, corresponding to the activated word line WL.
In FRAMs, data is destroyed by data-read operation. Namely, when data is read from a ferroelectric device, this data-read operation destroys the data that has been stored in the ferroelectric device. In the same manner as in DRAMs, therefore, data writing must be carried out as part of data-read operation with respect to a memory cell after data is read from the memory cell connected to the activated word line WL. Namely, both the word line WL and the plate line PL need to be activated in both the data-write operation and the data-read operation.
In the configuration of FIG. 1, the word lines WL and the plate lines PL extend over a wide span in the cell circuit 517. At the time of data-read operation or data-write operation, therefore, the word line WL and the plate line PL are activated not only with respect to a cell that is accessed for data reading or data writing, but also with respect to cells that are not being accessed. Because of this, electric power consumed.by the word line WL and the plate line PL is wasted.
As a simple and straightforward measure, the cell circuit may be divided into a plurality of blocks in the column direction, with a word-line driver and a plate-line driver being provided with respect to each block. In this case, however, the numbers of word-line drivers and plate-line drivers increases, resulting in an undesirable increase of chip size.
Accordingly, there is a need for an FRAM with reduced power consumption.
It is a general object of the present invention to provide a semiconductor memory device that substantially obviates one or more of the problems caused by the limitations and disadvantages of the related art.
Features and advantages of the present invention will be set forth in the description which follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description. Objects as well as other features and advantages of the present invention will be realized and attained by a semiconductor memory device particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a semiconductor memory device which includes ferroelectric memory cells, cell transistors connected between first nodes of the memory cells and data transfer lines, the memory cells and the cell transistors being grouped into units each corresponding to one or more column addresses, global word lines, one of which is activated in response to selection of a corresponding row address, global plate lines, one of which is activated in response to selection of the corresponding row address, local word lines, each of which is provided and dedicated for a corresponding one of the units, and is connected to gates of the cell transistors, local plate lines, each of which is provided and dedicated for a corresponding one of the units, and is connected to second nodes of the memory cells, and a unit switch circuit which electrically connects the activated one of the global word lines to one of the local word lines in a selected one of the units so as to achieve the same potential therebetween, and electrically connects the activated one of the global plate lines to one of the local plate lines in the selected one of the units so as to achieve the same potential therebetween.
In the semiconductor memory device described above, one or more column addresses constitute a unit, and a local word line is provided for each unit as a dedicated word line. Then, a local word line in a selected unit is connected to a global word line. Further, a local plate line is provided for each unit as a dedicated plate line. Then, a local plate line in the selected unit is connected to a global plate line. This makes it possible to activate a local word line and local plate line only in the selected unit, thereby avoiding excessive power consumption.
Moreover, it is another and more specific object of the present invention to provide a semiconductor memory device with a reduced test time. A need for such a semiconductor memory device will become apparent from the description of embodiments which follows.
In order to achieve the above object according to the present invention, a semiconductor memory device includes ferroelectric memory cells, bit lines which transfer data read from or written to the memory cells, cell transistors which connect between the memory cells and the bit lines, word lines which control on/off states of the cell transistors, word-line driving circuits which drive the word lines, precharge circuits which precharge the bit lines, and a timing control circuit which controls the word-line driving circuits and the precharge circuits to deactivate a word line prior to commencement of precharge operation in a first mode and to deactivate a word line after commencement of precharge operation in a second mode.
In the semiconductor memory device as described above, the word-line driving circuits and the precharge circuits are controlled so as to deactivate a word line after commencement of precharge operation in the second mode. When the cell transistors become nonconductive, therefore, the data voltages are already removed from the bit lines, so that the parasitic capacitance of the memory cells do not store electrical charge therein. An immediately following data-read operation can thus test the data-retention capability of the memory cells alone. There is no need to set aside a wait time after the data-write operation and before the data-read operation, being different from the case of the related-art test operation. This makes it possible to quickly conduct the memory cell test.